Re: Logic Minimization Algorithms

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Article #11043

#11043

From: Preston Briggs
Date: Tue, 15 Dec 1992 18:27

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roberts@angelo.amd.com (Dave Roberts) writes:
>
>I couldn't think of a more appropriate news group to post this in

comp.compilers comes to mind :-)

>What sort of algorithms are typically used to minimize logic equations
>specified in high level hardware description languages (PAL software,
>Verilog, etc.)?
>[...]
>So I guess my question is, how are these problems overcome?  Do people
>use other algorithms than Quine-McClusky instead that don't suffer
>these problems?  If so, what are they?
>
>Does someone have references of articles that describe this stuff?

Here's one, which has many pointers further back.

  author="Kurt Keutzer and Wayne Wolf",
  title="Anatomy of a Hardware Compiler",
  pages="95--104",
  journal=sigplan,
  year=1988,
  month=jul,
  volume=23,
  number=7

It's in the Proceedings of the SIGPLAN '88 Conference on
Programming Language Design and Implementation.

Preston Briggs

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From: preston@dawn.cs.rice.edu (Preston Briggs)
Subject: Re: Logic Minimization Algorithms
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Date: Tue, 15 Dec 1992 18:27:47 GMT
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