🚀 go-pugleaf

In article <1992Dec15.205639.25591@super.org> rminnich@super.org (Ronald G Minnich) writes:
>
>Actually, seems to me they could look at SCI. Except they want low cost.
>But if the CMOS chips for SCI pan out, maybe they will meet the cost 
>range.

We have received this response from several people.  We 
disagree.  For one SCI had a physical topology (a ring) that 
is not suitable for expansion I/O.  Yes, we know you can run 
the ring to and from the same board and create a topology 
that looks like the Anet (Compaq Proposal) topology but then 
you begin to loose much of the cost advantages.  We took a 
long look at SCI before we created our proposal.  We ran 
into lots of problems trying to allow different speed rings 
to work together and the biggest problem was that we didn't 
like having to have bi-polar transceivers.  When we started 
to recast the thing for CMOS implementation we ran into 
protocol inefficiencies and, well, it just didn't seem to 
work out the way we need it to.  The major thing turned out 
to be that SCI and the Compaq proposal (we call it Anet 
around here) were trying to solve different problems with 
cost, not bandwidth, being the major one.  The fact that the 
'C' in SCI stands for coherent I think brings out one of the 
differences in approach.  We needed an I/O interface and 
coherency in the I/O subsystem was something that we were 
trying to eliminate.  The address bandwidth required to 
maintain coherency in the I/O subsystem is prohibitive.

Don't get me wrong, we think that from a technical point of 
view SCI is neat.  It just seems to be intended for a 
different part of the system architecture.  We would welcome 
any comments you have to the contrary.  When/if you respond, 
tell us how we can make an SCI, I/O subsystem as cheap as an 
Anet, I/O subsystem.
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Christopher Simonich        simonich@twisto.compaq.com
Compaq Computer Corp.       [713] 374-1898
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