🚀 go-pugleaf

In article <1992Dec15.024904.22554@amd.com> roberts@angelo.amd.com (Dave Roberts) writes:
>
>I couldn't think of a more appropriate news group to post this in, so
>here goze:
>
>What sort of algorithms are typically used to minimize logic equations
>specified in high level hardware description languages (PAL software,
>Verilog, etc.)?
>
>I've read and understand Quine-McClusky, and doodled around with
>implementing my own versions.  It seems to work well except for the
>final step: choosing a set of prime implicants from the set that you
>just produced (by reductions of the form x * y + x * ~y = x, for those
>of you who don't remember.  Prime implicants are those product terms
>that can't be reduced any further by the application of the above
>identity).
>
Quine-McClusky is not used in CAD because you cannot handle logic
equations of the size that people want to do. Current methods 
are called algebraic, implying that the equations are never
fully expanded. 

Automatic translation from logic equations to gates has become popular
in the last few year and you will find a number of papers on the
subject in conference proceedings. Try Design Automation Conference
(DAC) proceedings, or International Conference on Computer Aided
Design (ICCAD) proceedings. Keywords to look for are Logic Synthesis,
Logic Minimization.


Michael Weaver.