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Article #11131

Re: RISC assemblers question

#11131
From: Richard Cownie
Date: Thu, 17 Dec 1992 17:39
51 lines
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masticol@cadenza.rutgers.edu (Steve Masticola) writes:
: Hi,
: 
: I've met a couple of people who have attempted to write assemblers for
: RISC machines, who say that it's a difficult job. Can someone give me
: an inkling as to why?
: 
: I'm not saying that it isn't; the reason just isn't obvious to me
: right now.
: 
: Thanks,
: - Steve (masticol@cs.rutgers.edu).

Writing a basic assembler for most RISC machines must surely be easy,
because the instruction formats are few and simple.  However, I can
think of several things which can make it harder:

  1) For a processor like the original MIPS, the assembler is responsible
     for identifying pipeline hazards and re-ordering the code and
     inserting no-ops to avoid them.

  2) For machines with delayed branches and suchlike, the assembler
     often tries to optimise by filling the delay slot.  I've just
     been looking at the Sun SPARC assembler, and it has a huge pile
     of peephole optimization code.

  3) In the quest for simplicity of the instruction set, some things
     usually get swept under the carpet and become difficult, e.g.
     loading immediate constants into registers.  Most RISC's implement
     the common cases of small +ve and -ve integer constants simply
     and efficiently, but loading a random 32-bit constant may be hard.
     On the SPARC, this takes 2 instructions, on the ARM, which is what
     I'm thinking of in particular, it could take up to 4 instructions,
     as immediate constants were only 8 bits shifted by any even number!
     Sounds bizarre, but actually it catches most of the common cases.
     Anyway, it's nice for the assembler writer to hide these kinds of
     architectural warts with pseudo-instructions.

     And then if the things you're loading is a relocatable address ...

So I guess the answer is, as for most software, you can get 80% of
the functionality with 20% of the work, but getting the last 20% is
hard.



-- 
Richard Cownie (a.k.a. Tich), Meiko Scientific Corp 
email: richard@meiko.com
phone: 617-890-7676
fax:   617-890-5042       
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Message-ID: <1992Dec17.173930.3235@meiko.com>
Path: arc1-ca.pugleaf.net!sparky!uunet!noc.near.net!meiko.com!richard
References: <Dec.17.10.16.36.1992.17493@cadenza.rutgers.edu>

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Path: arc1-ca.pugleaf.net!sparky!uunet!noc.near.net!meiko.com!richard
From: richard@meiko.com (Richard Cownie)
Subject: Re: RISC assemblers question
Message-ID: <1992Dec17.173930.3235@meiko.com>
Organization: Meiko Scientific Corp.
References: <Dec.17.10.16.36.1992.17493@cadenza.rutgers.edu>
Date: Thu, 17 Dec 1992 17:39:30 GMT
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