🚀 go-pugleaf

After reading the material available about the Alpha, I noticed that it was
mentioned a few times that the first implementation of the Alpha, the 21064,
is *super-pipelined* as well as superscalar.  For example, in "infosheet.txt"
that is available on gatekeeper.dec.com the following is stated:

>    Digital's 21064 Microprocessor
>    ....
>    The 21064 is a super-scalar, super-pipelined implementation of the
>    Alpha architecture. Super-pipelined means that an instruction is issued
>    to the functional units at every clock tick and the results are
>    pipelined. Being super-scalar, the architecture allows the instruction
>    unit to issue two instructions per clock tick, resulting in
>    significantly higher throughput and performance.

After reading the Data Sheet of the 21064, I find nothing that seems to
indicate the 21064 is super-pipelined, at least in terms of the common
definition of super-pipelined.  Is DEC redefining the word "super-pipeline"?
Anybody out there that can explain?

	Chris Perleberg
	pchris@dcc.uchile.cl