🚀 go-pugleaf

   From: masticol@cadenza.rutgers.edu (Steve Masticola)
   Date: 17 Dec 92 15:16:37 GMT

   I've met a couple of people who have attempted to write assemblers for
   RISC machines, who say that it's a difficult job. Can someone give me
   an inkling as to why?


Scheduling in the presence of span dependent instructions adds 
an interesting twist to writing an assembler for RISC machines.
This is particularly true for machines that require NOPs.

For example, consider:
		
		instr		; regular instruction
		sdi(Label_1)	; span dependent instruction
		instr		; regular instruction
		instr		; regular instruction
	
		...
	Label_1:

One would like to schedule the above sequence of instruction after
having expanded the instruction sdi(Label_1). Unfortunately, this
presents a chicken and egg scenario. One cannot expand the instruction
sdi(Label_1) unless one knows the value of the label Label_1. Further,
one cannot determine the value of Label_1 unless one schedules these
instructions and determines the number of NOPs required.

This problem is addressed in the SML/NJ compiler and is quite easily
solved. The sources are free with the SML/NJ distribution. Further,
this "assembler" is derived from a machine description and is
presently used in the MIPS, SPARC, HPPA, and RS6000 code generators
for SML/NJ. There is every reason to believe that it will readily
adapt to other RISC processors too.