🚀 go-pugleaf

In article <1992Dec31.013141.132685@zeus.calpoly.edu> mneideng@thidwick.acs.calpoly.edu (Mark Neidengard) writes:
>I think that the way of getting around this bottleneck is to use EXTENSIVE
>caching with sophisticated read-ahead logic.  I figure that a 200 MHz
>processor like the Alpha should be mated with 5 ns RAM in order to do "hot
>cycle" memory access, which is a practical impossibility.  So, like everyone
>else, they have waitstates and attempts at caching.  And the Alpha is only
>the tip of the iceberg.  If you got a chip that executes a lot of
>instructions at once (say, three or more in parallel sustained), just
>trying to keep the instruction prefetch pipelines filled would require more
>throughput than the memory bus could handle.  The only solution will have to
>be making faster memory, and caching to a farethewell until then.
>
>Don't be surprised if CPU's start coming out with 1 meg of onboard cache
>within the next year...


	Is this really likely, given the complexity (according to 
	net rumor) already involved in fabricating the Alpha?


>
>Mark Neidengard
>mneideng@cosmos.acs.calpoly.edu
>"You gotta concentrate on the mission you be takin'.
> It's not so much the mission, but you got crazy ignition!"
>           A Tribe Called Quest
>


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