🚀 go-pugleaf

RetroBBS NetNews Server

Inspired by RockSolid Light RIP Retro Guy

Article View: comp.arch
Article #11200

Re: RISC assemblers question

#11200
From: Josh Osborne
Date: Sat, 19 Dec 1992 00:19
52 lines
3040 bytes
In article <lj2h6hINNikj@exodus.Eng.Sun.COM> nand@not-and.Eng.Sun.COM writes:
[...]
>A couple of things make it a *little* harder :
>
>1) Branches with delay slots (you have to be able to represent them and
>   deal with them).

If the assembler isn't attempting to re-order code then it doesn't need
to know about this (except for #4).

>2) In general, chip workarounds are done in the assembler, and this code
>   is just yuckier to deal with

I don't know.  I think it is yucker to deal with
MOVE.L D0,(A0+D1*4+12)		# Sort of a 68020 instruction
(move D0 to Mem[A0 + D1*4 + 12], and worse addressing modes exist!)
Or the fact that ADD AX,anything is diffrent from ADD (non-AX-reg),anything.
And that only some addressing modes are available on some OPs.

Or at least about as yucky.

>3) branches have limited scope (on SPARC, you get only 22 bits in the branch
>   instruction). It is reasonable to leave a check in the assembler to detect
>   branches to targets that are larger than the displacement will allow.

Branches on most boxes have limited scope.  However JUMPs and CALLs on
RISCs have limited scope (for the immediate mode instructions) if you need to
deal with external linkage then this could be a problem.  If not it is no
harder then the Bcc OPs on the 680x0 (or 6502!).

>4) Code to check architectural correctness (try doing something illegal
>   with the SPARC assembler - if it sqawks, then someone had to write the code 
>   to do the check). This is very important, because the machine will not always
>   execute "arbitrary assembly language". 

Yes, but it is also hard for CISC assemblers to support a whole family of
similar CPUs (68020 has more addressing modes then the 68000, the 80386
supports WAY more instructions in 32bit mode then the 8086...).  However I
think the CISC assemblers do this easyer then RISCs do #4.

>There may be others, these are the only ones that come to mind right now. 

Could be, however I think that unless you try to make the RISC assembler
optimise they are both about as hard to write (and if you make the CISC
assembler opt. also, then I don't know which is simpler!).
[...]
-- 
           stripes@pix.com              "Security for Unix is like
      Josh_Osborne@Real_World,The          Multitasking for MS-DOS"
      "The dyslexic porgramer"                  - Kevin Lockwood
We all agree on the necessity of compromise.  We just can't agree on
when it's necessary to compromise.       - Larry Wall
Technical Details
Message-ID: <BzHCvw.CAM@pix.com>
Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!darwin.sura.net!mojo.eng.umd.edu!pandora.pix.com!stripes
References: <1992Dec17.173930.3235@meiko.com> <lj2h6hINNikj@exodus.Eng.Sun.COM>

Show Full Headers
Complete Article Headers
Newsgroups: comp.arch
Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!darwin.sura.net!mojo.eng.umd.edu!pandora.pix.com!stripes
From: stripes@pix.com (Josh Osborne)
Subject: Re: RISC assemblers question
Message-ID: <BzHCvw.CAM@pix.com>
Sender: news@pix.com (The News Subsystem)
Nntp-Posting-Host: pandora.pix.com
Organization: Pix Technologies -- The company with no adult supervision
References: <1992Dec17.173930.3235@meiko.com> <lj2h6hINNikj@exodus.Eng.Sun.COM>
Date: Sat, 19 Dec 1992 00:19:06 GMT
Lines: 52