Article View: comp.arch
Article #11241Re: specks for the intel P5
From: John West
Date: Sun, 20 Dec 1992 13:02
Date: Sun, 20 Dec 1992 13:02
15 lines
1278 bytes
1278 bytes
awolfe@moo.Princeton.EDU (Andrew Wolfe) writes: >This is not quite true. Intel has presented limited P5 details at Hot-Chips >and at the Microprocessor Forum. Pentium will be a Superscalar >implementation of the X86 instruction set. It is a single integrated CPU - >not a RISC chip with a 386 tagged on. It will run 368 and 486 user code as >is. Someone posted some numbers here a while back. A 33MHz external/66MHz internal part was claimed to run at 30-40 MIPS. Meaningless enough for you? Sounds about right. Superscalar, and they still can't get 1 instruction/cycle. John West -- For the humour impaired: Insert a :-) after every third word
Technical Details
Message-ID:
<1h1qseINNdi@uniwa.uwa.edu.au>Path:
arc1-ca.pugleaf.net!sparky!uunet!ferkel.ucsb.edu!taco!rock!stanford.edu!ames!think.com!rpi!batcomputer!munnari.oz.au!uniwa!johnReferences:
<KAY.92Dec3141439@kauri.kauri.vuw.ac.nz> <Byp0KC.EAB@csfb1.fir.fbc.com> <id.1UJV.ZIE@ferranti.com> <1992Dec8.045715.5648@wam.umd.edu> <Bz1w3v.3KL@dscomsa.desy.de> <1992Dec10.173235.1931@Princeton.EDU>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!ferkel.ucsb.edu!taco!rock!stanford.edu!ames!think.com!rpi!batcomputer!munnari.oz.au!uniwa!john From: john@gu.uwa.edu.au (John West) Newsgroups: comp.arch Subject: Re: specks for the intel P5 Date: 20 Dec 1992 13:02:06 GMT Organization: The University of Western Australia Lines: 15 Message-ID: <1h1qseINNdi@uniwa.uwa.edu.au> References: <KAY.92Dec3141439@kauri.kauri.vuw.ac.nz> <Byp0KC.EAB@csfb1.fir.fbc.com> <id.1UJV.ZIE@ferranti.com> <1992Dec8.045715.5648@wam.umd.edu> <Bz1w3v.3KL@dscomsa.desy.de> <1992Dec10.173235.1931@Princeton.EDU> NNTP-Posting-Host: mackerel.gu.uwa.edu.au