🚀 go-pugleaf

In article <BxL3IH.KtH.2@cs.cmu.edu> lindsay+@cs.cmu.edu (Donald Lindsay) writes:
>In article <15445@auspex-gw.auspex.com> guy@Auspex.COM (Guy Harris) writes:
>>Hmm.  As I remember, somebody from DEC at a session on topics such as
>>OSF/1-on-MIPS on Tuesday night at the San Antonio USENIX claimed that
>>HP-PA was "out of gas"; ...
> ...
>
>What he may have meant, is that HP won't be able to use offchip
>primary cache much longer. That was difficult at 66 MHz, and is
>really impressive at 100 MHz. Even HP can't do it at 200 MHz, surely. <---
> ...
>
>Don		D.C.Lindsay 	Carnegie Mellon Computer Science

A person from HP previously addressed your incredulity regarding 
the feasibility of 200MHz off-chip caches:

#From: linley@hpcuhe.cup.hp.com (Linley Gwennap)
#Newsgroups: comp.arch
#Subject: Re: Re: Offchip Primary Cache
#Message-ID: <32580093@hpcuhe.cup.hp.com#
#Date: 5 Mar 92 21:46:37 GMT
#References: <1992Mar03.233219.176162@cs.cmu.edu#
#Organization: Hewlett Packard, Cupertino
#
#(Donald Lindsay) discusses HP cache access rates:
#> I'm impressed that HP can do it at 100 MHz. Can you do it at 200 MHz?
#
#There is no reason to believe that 200 MHz will not be possible. 100 MHz
#primary caches on the PA7100 are accomplished with standard PCB technology,
#ceramic PGA packaging, and off-the-shelf 9ns TTL I/O SRAMs. SRAMs get 
#faster every year, multichip modules are getting cheaper, ECL I/O circuits
#are well understood, future VLSI technologies will improve timing 
#overhead, etc, etc.  Two years ago these same discussions were taking place
#about whether external primary caches could ever run at 50 MHz.
#
#Some of the work going on to define new high-speed I/O protocol standards
#for DRAM and SRAM memory devices also look interesting for application
#in future cache memory designs. 
#