🚀 go-pugleaf

eoahmad@ntuix.ntu.ac.sg (Othman Ahmad) writes:
: Darren R. Davis (drdavis@u.cc.utah.edu) wrote:
: : I have been pondering an idea for a machine architecture.  A processor
: : that has no registers.  I am familiar with some architectures that have
: : done this.  My twist on this theme is to have a very large cache on chip
: : for memory locations (effectivelly becoming registers).  This goes
: : against the RISC idea of having very large register sets with load store
: : instructions.  This machine would just reference memory, and the most
: : common addresses becoming cached internally to the processor giving very
: : fast access.  Does anyone know of such a machine, and what are your
: : thoughts on this kind of architecture.  I envision the cache being
: 
: I have been thinking about this for some time now.
: First, you have broken the law as stated by H&P book.
: The major problem that you have to face is the large number of address bits,
: required to access your data. 32-bit per operand is rather large.
: 
: To solve this you have 2 choices:
: 
: i) stacks,
: ii) data compression,

The Inmos Transputer has very few registers (you still need a program
counter, don't you?) but has 4K of onboard memory. One of the registers
is a workspace (aka stack frame) pointer, and offsets 0 - 15 can be accessed
by a 1-byte instruction (4 bit opcode, 4 bit offset) with every extra 4 bits
of offset costing an extra byte. Does this fit the bill?
Also see "Register Allocation for Free: the C Machine Stack Cache" by
Ditzel & McLellan (ACM ASPLOS I, Mar 1982) which makes some good points
about registers vs. caches.
-- 
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