🚀 go-pugleaf

rsnider@xrtll.uucp (Richard Snider) writes:

>The PDP-10 could fall into this classification without too much arguing.
>It had its set of 16 general purpose registers defined simply as the
>first 16 locations in memory.  Naturally, they implemented the the
>"registers" as logic (register files) rather than core (in the first
>ones).  The secret way to get your program to run really fast in
>a tight loop was to load it into the registers (up to 16 instructions)
>and then jump to one of the registers......

"Fast memory" (accumulators as logic) was optional on the PDP-6 (a PDP-10
predecessor) and perhaps the KA10 also (I'm sure most KA10's did have it).
Moving code into fast memory was useful on the -10 (and -6) processors without
cache; MACRO-10 supported the practice by allowing sections of code to be
relocated (by the linker) for residence in fast memory (but the user had to
BLock Transfer (BLT) the code into fast memory and jump to it).  On PDP-10
processors with cache (the KL10 and KS10), it was better to keep tight loops
out of fast memory.

Sadly, the dual use of locations 0-17 as accumulators and memory helped doom
the -10 ISA... it created a potential data hazard between instructions using
an accumulator and any instruction which might be referencing that accumulator
as memory...  this made it very difficult to pipeline or micropipeline (even
worse than the VAX).

--
John R. Grout						j-grout@uiuc.edu
University of Illinois, Urbana-Champaign
Center for Supercomputing Research and Development