🚀 go-pugleaf

In article <lgnfc3INNqnt@spim.mti.sgi.com>, woodacre@mips.com (Michael Woodacre) writes...
>In article <1992Nov18.210416.27212@nntpd.lkg.dec.com>,
. . .
>Can you explain how this is different from kernel code with interrupts
>disabled on any other risc processor? For instance, an R4000 can
>implement uniprocessor-atomic "instructions" which are sequences of
>MIPS instructions to implement complex functions by running code
>in kernel level with interrupts switched off.

There are certainly similarities. PALcode "instructions" actually appear
as single instructions in the Istream which is handy for debuggers, etc.
PALcode runs with interrupts disabled, Istream memory management traps
disabled, and complete control over machine state. The environment allows
more flexibility and more possibilities than merely running in the "standard"
environment with interrupts disabled.

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Steve DiPirro        dipirro@star.dec.com
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