🚀 go-pugleaf

In article <1992Nov19.204612.10316@odin.diku.dk> thorinn@diku.dk (Lars Henrik Mathiesen) writes:
1st> I suspect
1st> that PA-RISC can get by with executing fewer instructions as well.
2nd> This is, in a nutshell, the CISC viewpoint.
3rd>Some might call it engineering. 
 
1st>                  I was clearly describing the HP-PA architecture as
1st>being placed firmly within the RISC sphere, albeit in the less
1st>aggressively hardware-optimizable end.
1st>
1st>Rather than snide remarks, I had hoped to elicit informed comment as
1st>to how much the statefulness of the HP-PA programmers' model impacts
1st>(or can be assumed to impact) current and future implementations, in
1st>development time *and* in achievable speed for a given technology.
1st>
1st>Please?

Let me try.

First of all, I do not think I know both architecture and VLSI enough to call
PA-RISC being in the "less aggressively hardware-optimizable end." However,
I suspect that current PA-RISC is not too complex to design with the advent of
the state-of-the-art logic/layout synthesis. Using advanced EDA tools, I think 
it is possible to design a new RISC layout more complex than PA-RISC and 
still achieve fast-time-to-market and price-competitive dies. People may have
to use full/semi-custom design styles instead of gate-array though.

1st>
1st>Lars Mathiesen (U of Copenhagen CS Dep)<thorinn@diku.dk> (Humour NOT marked)

KJ "Not a PA-RISC designer" Chang
-- 
K J Chang, Hewlett-Packard ICBD R & D,                      (())_-_(())
Palo Alto, CA 94304                                          | (* *) | 
Internet: kjchang@hpl.hp.com           a UCLA Bruin  -->    {  \_@_/  }
voice mail: (415)857-4604                                     `-----'