Article View: comp.arch
Article #11324Re: DEC Alpha AXP System INTEGER Performance
From: Mark Forsyth
Date: Thu, 19 Nov 1992 17:28
Date: Thu, 19 Nov 1992 17:28
39 lines
2539 bytes
2539 bytes
In comp.arch, blair@snogum.enet.dec.com (Blair Phillips - Digital) writes: > > A good example is the lack of 8 and 16 bit load and store instructions. > Providing these would have added a complex multiplexor in the critical path > from the internal cache to the register file. It would have forced either a > longer cycle time, or an extra cycle for *all* load/store instructions. I've been hearing about this claimed architectural advantage for months now but still don't get it. For example: 1) why is the cache to register file path so critical in the alpha chip ? this is not the case with all microprocessors. especially the store path - I thought that address generation was usually tougher. is this another "superpipelining" dividend ? 2) multiplexers can be made VERY fast - they only add a transfer gate and wire delay in the data path (or you can just use the transfer gate already needed for the register input). why not just speed up this circuit, or take a slight amount of time from the cache access (should be easy with on-chip primary cache) or register setup time ? or add another transparent data latch in front of the multiplexer so it can be done in a different clock cycle ? perform the multiplexing in existing cache circuits ? (your idea here) ? 3) is it really forward looking to modify the instruction set because one circuit design had trouble meeting its speed budget ? isn't it conceivable that other implementations won't have the same critical speed path ? Do other processor designers see any fundamental speed advantage for alpha due to this decision ? Alpha certainly is fast, but I would guess that this is due more to the long pipeline, the special VLSI technology DEC developed, a willingness to sort out the very fastest parts in the speed distribution for the mainframe version (even DEC says 200MHz is not available "in volume") and good circuit designers rather than instruction-set wizardry. It is unfortunate that marketeers can't be satisfied with just good engineering. - Mark Forsyth (my opinions, not HP's) maf@fc.hp.com
Technical Details
Message-ID:
<8840086@hpfcso.FC.HP.COM>Path:
arc1-ca.pugleaf.net!sparky!uunet!wupost!sdd.hp.com!hpscit.sc.hp.com!scd.hp.com!hpscdm!hplextra!hpfcso!mafReferences:
<1698@niktow.canisius.edu>Show Full Headers
Complete Article Headers
From: maf@hpfcso.FC.HP.COM (Mark Forsyth) Date: Thu, 19 Nov 1992 17:28:29 GMT Subject: Re: DEC Alpha AXP System INTEGER Performance Message-ID: <8840086@hpfcso.FC.HP.COM> Organization: Hewlett-Packard, Fort Collins, CO, USA Path: arc1-ca.pugleaf.net!sparky!uunet!wupost!sdd.hp.com!hpscit.sc.hp.com!scd.hp.com!hpscdm!hplextra!hpfcso!maf Newsgroups: comp.arch References: <1698@niktow.canisius.edu> Lines: 40