🚀 go-pugleaf

In article <1ho4g1INNgac@nigel.msen.com>, paulh@msen.com (Paul Haas) writes:
|> Bob Supnik (supnik@human.enet.dec.com) wrote:
|> 
|> : The ingenuity of processor designers (and semiconductor technologists) being
|> : far from exhausted, I believe this performance growth can continue for the
|> : rest of this decade.  There are some limiting factors:
|> 
|> : - Process technology evolution appears to be slowing somewhat, due to
|> :   lengthening development time (and cost) for new generations of semiconductor
|> :   processing equipment.
|> 
|> Is this a long term trend?

[begin sepculation]

I doubt it. In the past the slowing down of process technology evolution has
lead to process technology revolution. As the rate of improvement in
lithography slows down, people will just start looking towards new
technologies and begin building into the third dimension. There are certainly
many technologies out there which are just waiting for somebody to do the
research to make them more affordable.

Additionally, now that voltage is scalling with device size, total CMOS
performance (speed/area) is inversely proportional to the third power of
lithography line size, not the fourth power as used to be the case. That
means that the threshold at which it becomes more profitable to spend money
on 3D devices than on smaller lithography has become considerably smaller.
If cheap sub-micron fabrication is as difficult as people have been saying,
process people will just head upwards.

[end speculation :-) ]

I have a question along those lines. If (as I have been led to believe) there
exists a linewidth which is large enough for yield to be effectively 100%,
why hasn't anybody attempted to build a very tall, large line width chip?

Is the problem a difficulty in creating monocrystaline Si above the substrate?

Are problems with planarization cumulative such that working with too many
levels becomes impossible?

Or is there another reason?

Thanks.

Jason W. Solinsky