🚀 go-pugleaf

moss@cs.cmu.edu (Eliot Moss) writes:

>In fact, conditional
>instructions are easy to handle in a regular pipeline -- you just suppress the
>store in the last step, and you certainly know the outcome of the comparison
>by then. In a superscalar, where things get reordered, it is admittedly not
>quite so simple.

But neither are conditional branches. I would like to see a
superscalar architecture that handles conditional branches by a
mechanism that could not also be used (or simplifyed) for conditional
moves or arithmetic. If need a conditional instruction on an ARM or
Alpha, you certainly will need a conditional branch on "normal" RISCs.
Looking for conditional branches in the pipeline is no easier than
looking for conditional instructions in general, especially on the
ARM, where the first 4 bits determine (uniformly) if the instruction
is conditional.

	Torben Mogensen (torbenm@diku.dk)