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Article #11406

Re: Hardware support for atomic operations ?

#11406
From: David Gustavson
Date: Sun, 22 Nov 1992 22:35
42 lines
2713 bytes
In article <1992Nov21.173146.7509@ncsu.edu>, odkahn@eos.ncsu.edu (OPHER
DANIEL KAHN) wrote:
> 
> I am interested in primitives that support mutual exclusion in hardware, such
> as the Test-And-Set and Swap instructions which are atomic.  I am especially
> interested in any such new primitives that may have been developed in the
> last few years.  If you know of any good references I would appreciate
> some e-mail!
> -- 
>  Opher D. Kahn 

The Scalable Coherent Interface project spent a lot of effort on this
subject, because it needed to find mutual exclusion primitives that work
well in a large distributed multiprocessor with rather arbitrary
interconnect. SCI (now IEEE Std 1596-1992) settled on Swap, Compare & Swap,
and Fetch & Add as its base set, with the operation being exported to the
addressed memory controller or device for atomic execution there, and the
result returned to the processor via the same interconnect. 

There is some overview of this in an article on SCI in Feb 92 IEEE Micro,
pp 10-22. This work also was supported by IEEE Std 1212-1991 Control and
Status Register (I/O) Architecture and some related work on standard DMA
(multiple processors feeding DMA work queues and multiple DMA engines
reporting status to a processor via completion queues (interrupt service
queues). 

A nice reference about the power of various locks is Herlihy, M. Γ’Wait-Free
Synchronization,Γ“ ACM Transactions on Programming Languages and Systems 13,
1 (Jan. Γ•91) 124Ð149. 

Other references I recommend include Mellor-Crummey, J.M. & Scott, M.L.
"Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors,"
ACM Transactions on Computer Systems 9, 1 (Feb '92) 21-65; and
Mellor-Crummey, J.M. & Scott, M.L. "Synchronization without Contention,"
ASPLOS-IV April 91 procedings.

--------------------------------------------------------------
-- David B. Gustavson, Computation Research Group, SLAC, POB 4349 MS 88,
    Stanford, CA 94309   tel (415)961-3539  fax (415)961-3530
-- What the world needs next is a Scalable Coherent Interface!
-- Any opinions expressed are mine and not necessarily those
   of the Stanford Linear Accelerator Center, the University, or the DOE.
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From: dbg@slac.stanford.edu (David Gustavson)
Subject: Re: Hardware support for atomic operations ?
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