🚀 go-pugleaf

In article <By4pEI.8r5.2@cs.cmu.edu> lindsay+@cs.cmu.edu (Donald Lindsay) writes:
>andrew@megadata.mega.oz.au (Andrew McRae) writes:
>>If it looks like microcode, smells like microcode ... Why call it PALcode?
>
>Because it doesn't even vaguely resemble microcode.
>
>- PALcode is fetched from the I-cache, not from ROM.
>- PALcode is decoded by the normal decoder, as opposed to to microcode,
>  which is often a raw mask over a processor's internal control lines.
>- Microcode is usually in charge of detailed sequencing/timing of e.g. 
>  register writebacks. PALcode has no concept of this, except for
>  some implementation-specific rules like "if you set this TLB control
>  register, then the TLB mode will change one clock later".

I know of at least one other Intel processor using micro-code with
these properties. But then, Intel is a CISC dinosaur doing reactionary
evil things so it is micro-code; on the other hand, DEC (at least the
NEW DEC) is a forward looking RISC convert so it's the sexy PAL-code.

Actually, I believe there is a distinction:

  The PAL-code is not part of the architecuture.

This means one can have a VMS-Aplha and a Unix-Alpha, etc. and most
of the system is still portable. Think of PAL-code as a "O/S dependent
Hardware Abstraction Layer"

--
Stanley Chow            InterNet: schow@BNR.CA
Bell Northern Research  UUCP:     ..!uunet!bnrgate!bqneh3!schow
(613) 763-2831
Me? Represent other people? Don't make them laugh so hard.