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Article #11427Re: DEC Alpha AXP System INTEGER Performance
From: Dileep Bhandarkar
Date: Mon, 23 Nov 1992 13:29
Date: Mon, 23 Nov 1992 13:29
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In article <1992Nov20.220615.7494@raid.dell.com>, samf@yosemite.dell.com (Sam Fuller) writes... >After reviewing the Alpha performance claims, I had the feeling that the integer unit >did not really run at 133Mhz. It looked to me that the floating point pipeline was >superpipelined at 133Mhz, but that the integer side ran at a more reasonable 66Mhz. The >pipes can operate independently and I imagine be dispatched in parallel, hence the >superscalar appelation. In my opinion, either DEC did a terrible job of code scheduling >for their integer pipeline or its not really running at 133Mhz or 200Mhz as the case may >be. > > > >Anyone who knows care to comment on this analysis? > This is not true. The cpu is capable of issuing 2 instructions every cycle. Floating point is fully pipelined as is the integer unit. Integer shifts take 2 cycles; integer add/sub and logical ops take one cycle. Dileep
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Newsgroups: comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!darwin.sura.net!haven.umd.edu!decuac!pa.dec.com!nntpd2.cxo.dec.com!nntpd.lkg.dec.com!ryn.mro4.dec.com!wrksys.enet.dec.com!bhandarkar From: bhandarkar@wrksys.enet.dec.com (Dileep Bhandarkar) Subject: Re: DEC Alpha AXP System INTEGER Performance Message-ID: <1992Nov23.182714.27355@ryn.mro4.dec.com> Sender: news@ryn.mro4.dec.com (USENET News System) Organization: Digital Equipment Corporation References: <1992Nov10.153629.27510@ryn.mro4.dec.com> <martin.721554717@bert> <1992Nov12.101520.2828@crl.dec.com> <1698@niktow.canisius.edu> <jdd.721687838@cdf.toronto.edu> <1992Nov20.220615.7494@raid.dell.com> Date: 23 NOV 92 13:29:59 Lines: 19