🚀 go-pugleaf

In article <9245@idunno.Princeton.EDU> ssr@stokes.Princeton.EDU (Steve S. Roy)
asks:
   Is it my imagination or is it true that while the storage capacity of
   dynamic RAM chips has increased by orders of magnitude the speed has
   not? 

   Is it a fundamental VLSI level constraint that keeps the cutting edge
   memories at a particular speed?  If you consider a chip that has a
   given fraction of the storage of a cutting edge chip, will it have a
   predictable fraction of the response time?

   Is it that the people making chips (driven by the people buying chips)
   feel that the current speeds are 'good enough' and the main limitation
   is size, and therefore most of the effort goes toward greater density
   rather than greater speed?  Do the designers, or whoever makes the
   decisions, figure that 'If they really want something faster then
   they'll pay for static RAM?'


I am not sure I have direct answers to all your questions, but here is
a perspective on what happens and why in the DRAM business.

Memory density quadruples every 3 years. The majority of this increase
comes from lithography. That is, the cell size (one pass transistor and
one capacitor) gets smaller. There is also some help from the increase in
chip area. This is a double whammy for yield, one because the process is
getting more complex due to the finer and more exotic (see below) geometries
and second because the chip area is larger (yield is ~ e^(-lambda*Area)).

The cell size must get smaller, but the cell capacitance cannot.
Why? 
You need a large enough cell capacitance to guard against soft errors due
to radiation. That is you need to store at some minimum number of electrons
per cell. These days this number is in the few tens of thousands of electrons.
The second reason you need a certain minimum charge is to be able to drive
enough of charge onto the bit line. The cell state is sensed by charge sharing
between the dinky cell capacitance (~ 50 fF) and the huge bit line capacitance
( ~ 1 pF). 

Exotic geometries:
The upshot of the above paragraph is that you need a certain minimum capacitor
area while the cell area needs to keep shrinking. The way this has been 
recently been done is using the third dimension. The cell does not look planar
anymore. You either have deep "trenches" etched (not "dug") into the silicon
substrate or you have "stacks" raised on top of the cell to provide capacitor
area. This is precisely the kind of processing exotica that makes DRAMs so
expensive to develop. And of course there are ever more complicated device
issues, cell leakage, reliability of the capacitor oxide ...

Speed:
Very roughly
Memory access time =   time spent in the decoders (1)
                   + time spent to drive the word line (2)
                   + time the dinky cell takes to drive the bit line (3)
                   + time taken for column select and sensing (4)
                   + other misc stuff before your bit is on the pins (5)

(1) decreases with each technology generation (faster transistors) but
increases because there is more decoding to be done in the larger DRAM
(2) decreases because of faster transistors but increases because word lines
get longer because of the larger RAM array (remember chip areas are increasing)
(3) DRAM cell designers kill themselves to keep cell capacitance constant.
(see above) Bit line capacitance is increasing because of the larger array.
Overall, there is a slight increase.
(4) same as (1)
(5) constant

The result? Total delay is constant.

Now if you were to use the lithography levels of a 4M DRAM to make a 1M
DRAM, you certainly would have a smaller access time.
This access time would however not compare with that available with an
SRAM (I hope it is clear why SRAMs are faster than DRAMs).

The market seems to want ever larger DRAMs. Delivering that has been feat
enough. Speed has remained constant for the reasons mentioned above. 

There are however some innovations coming around. Some that I like
personally

1. Cache DRAMs: DRAMs with an on chip SRAM cache[1]. This looks to the
outside world as a large memory (say 4Mbit) with an SRAM like average
access time (say 10ns). 

2. BiCMOS DRAMs: allows one to further decrease delays (1),(2),(4),(5)
by using bipolar transistors. The down side is the added process complexity.

If the market demands it (ie pays for it) I would say we can have a research
prototype of a 16Mbit 5ns BiCMOS cache DRAM today. (you may realize I have
my fantasy hat on)

Prasad