🚀 go-pugleaf

In article <GLEW.91May7175310@pdx007.intel.com> glew@pdx007.intel.com (Andy Glew) writes:
>Just blueskying, but:
>
>    The biggest advantage of vector instructions is that they convey
>to the memory system the access pattern.  You have to add a lot of
>logic to your memory buffers to detect patterns beyond the simple "the
>next address is a stride of 64 past the previous" address

>    Most vector implementations are pipelined, not element-by-element
>parallel.  It isn't too hard to do superscalar/superpipelined
>implementations of scalar instruction sets that obtain parallelism
>comparable to most vector implementations. Multiple memory ports get
>harder, but are doable. But the access pattern info isn't there.
>

>    So: why not combine vector memory access instructions that convey
>access pattern, with scalar computational operations?
>
-
>
>Andy Glew, glew@ichips.intel.com
>Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, 
>Hillsboro, Oregon 97124-6497


Check out the article "The WM Computer Architecture" by Wm. (Bill) Wulf
(I believe it appeared in CAN circa early 1988).

He descibes an interesting multi-op/instruction load/store architecture
(RISC-like) based on a producer/consumer model,
with special "Streaming" (his terminology) loads and stores which enter fifo queues. 

The semantics are 
      Sin.size fifo#, stride, base, count
      Sout.size fifo#, stride, base, count

As Wulf notes: "The similarity of streaming to 'vector load/store'
operations should be apparent, and the rationale for its existence
is similar -- it reduces the number of instructions in loop bodies
and signals predictable reference patterns to the memory system."


All in all a very interesting paper...

Bill Moyer				insert disclaimer here --> <>
Senior Paleontologist / MC88110 design
Motorola Microprocessor Products Group