🚀 go-pugleaf

In article <3407@spim.mips.COM> zalman@mips.com (Zalman Stern) writes:
| In article <2496@cybaswan.UUCP> ex2mike@cybaswan.UUCP ( m overton) writes:
| >
| >A simple answer to all the problems with byte order etc, to the
| >authors mind, is to have a duplicate set of load and store instructions.
| >Since most RISC machines have very few of them, adding a set for the
| >opposite sense would surely be very easy. It wouldn't work with 
| >instructions, of course, but I assume that is not a problem. 
| >
| 
| No, it doesn't help at all. Current RISC chips which support bi-endian
| operation simply xor a constant with the low order address bits on non-word
| operations. The constant changes depending on the byte-order bit. Storing a
| word, changing the byte order bit, and loading the same word will get
| exactly the same value (it will not be byte swapped).  Words have a
| constant format in memory and byte addresses are modified appropriately.

Hmmm... I was under the impression that the 88K actually did swap
bytes around when switching between big and little endian.  The way
they do it, byte0 is always in the same location in 32-bit memory,
where the way the 29K (and apparently MIPS) does it, bit0 is always in
the same location, but the numbering of bytes changes:

	29K, MIPS				88K

        31              0                       31              0
	+---+---+---+---+			+---+---+---+---+
	| 0 | 1 | 2 | 3 |	Big Endian	| 0 | 1 | 2 | 3 |
	+---+---+---+---+			+---+---+---+---+

        31              0                        7-0    23-16
	+---+---+---+---+			+---+---+---+---+
	| 3 | 2 | 1 | 0 |     Little Endian	| 0 | 1 | 2 | 3 |
	+---+---+---+---+			+---+---+---+---+
						    15-8    31-24


Can someone from Mot confirm this?  What about some of the other
bi-endian processors out there (i960, i860)?

--
	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)