🚀 go-pugleaf

als@bohra.cpg.oz.au (Anthony Shipman) writes:
>I read a while back that one improvement being considered for large dynamic
>RAMS was removing the multiplexing of the row and column addresses, saving
>some time.  Is this still on the cards?


See the Hitachi HM571000 parts.  35/40/45 ns,  1 M by 1 BiCmos dram.

It uses a non-multiplexed address bus.  The down side is that it comes in
a 28 pin package (300mil SOJ) rather than the 18 pin DIP, 20 pin ZIP etc
that a standard 1 M by 1 dram comes in.  Going from 10 address lines to
20 lines tends to do this. (i.e. board area goes up.)


What nobody has mentioned is that increasing the density of memory devices
while holding the access time constant has a significant effect on the access
time for a memory array of a constant size.  Since you are driving fewer drams,
the transmission line effects are reduced and overall access time comes down.

The problem is that the amount of memory that people expect keeps increasing
at the same rate as the density increases....