🚀 go-pugleaf

Variant Instruction Set Computers - VISC
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A way to speed up future Motorola CISC MPUs could be:

Widen data bus to 64 bits and make the internal data paths and
ALU width all 64 bits.  Introduce an exclusive mode switch instruction
which would switch in an enhanced, RISC-like micro-engine, with totally
new instruction set geared for 64bit operations.  Superset the existing
16 x 32bit register file up to a n x 64bit register file so that the new
64bit mode could access the old style register file as part of the new,
large register file.  Access to FPU, cache and MMU ( and any other funct-
ional units ) would be maintained transparently as well as employing the
same pipeline stages ( this would be harder to do .. ) as the old CISC
core.  Notice that the RISC-like enhancements to the CISC core should 
be dropped and the CISC core kept for downward compatibility only - all
speedy execution should be handled by the RISC core.

This opens up the interesting option of, say implementing a SPARC RISC
core, or a HP-PA core, which would mean that an existing 680x0 product
would run HP-PA code on executing the mode switch instr.

This would mean that new compilers would have to be written which would 
be able to switch the MPU into the new mode for enhanced performance.  I
would think that this mean a addition CCR bit but since there are slots
available, it should be no problem.

What I do not like about this scheme is that it is resorting to kludging in
the same fashion that intel used to upgrade their 8080 to 80486 by adding 
bits and pieces which destroyed the orthogonality of the original design
( except that the 8080 wasn't a great design ).  The mode switch should
be possible without having to reset or destroy data in the CPU as opposed
to the real <-> protected mode switch horrors of the 80x86's.

Comments please ... ( flames to /dev/null )

BJ McDonald, University of Natal, Durban, King George V Ave, South Africa.