🚀 go-pugleaf

preston@ariel.rice.edu (Preston Briggs) writes:
>>The i860 can smoke a Sparc, but it takes a smart (mostly non-existant)
>>compiler and the right applications.  A man at Alliant charactarized
>>the 860 as having a small "sweet spot".

brooks@tazdevil.llnl.gov (Eugene D. Brooks III) writes:
>The "sweet spot" of the i860, 4 K bytes, is indeed very small.

By sweet spot, I would include more than just cache (which is 8K btw).
If the application is not FP intense, then you're wasting a good
portion of the chip.  If it's DP, you give up a factor of 2 in
multiplication rate.  If it's not balanced in FP adds and multiplies,
you give up further big chunks.  You also need fair-sized loops
to help mitigate the long latencies associated with the pipelines.
And, if there's inadequare reuse of data, you're going to be bound
up by cost of memory accesses (for example, when adding 2 long vectors).
Note that larger caches are no help if there's no reuse.

>By then, the i860 and all the other micros lacking some form of explicit
>vector functionality to saturate the available memory bandwidth will be
>fodder for lawn sprinkler controllers.

But the 860 (and RS/6000 and HP's machines) can easily saturate the
available memory bandwidth!  What we want is more bandwidth or paths
to memory or something to keep up with the FP.  Of course, this is
all expensive.

>That the chip is so difficult to compile for indicates a
>poorly designed architecture.

Perhaps so.  But weren't vectors machines considered difficult targets
for years (aren't they still)?  And consider the difficulties
compilers have had with parallel machines of all sorts.
The 860's just a new and interesting problem.

The RS/6000 and HP-snakes spend more hardware on the implementation
and are able to have a cleaner and simpler architecture (an approach
I support), but the 860 is still faster in some cases
(say, multiplication of large matrices).

Preston Briggs