🚀 go-pugleaf

 $@"((JIn <1991May16.182143.15390@murdoch.acc.Virginia.EDU>
	clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman) said:

Clark> The April 29, 1991 EE Times, page 16, mentions a 33-MHz TRON micro
Clark> from Fujitsu that supposedly runs at 32 MIPS. No benchmark explanation.
Clark> It is not intended for workstations, so we will probably never see
Clark> SPEC results for it, and it won't be sold in the U.S. But I am curious
Clark> to find out if anyone knows anything about the chip and the extremely
Clark> high ratio of 32 MIPS to 33 MHz for a CISC chip. It has an on-chip cache
Clark> of 2 KB and is described as "a five-pipeline CISC processor" that is
Clark> "capable of multitasking", "32-bits", and "developed to run the TRON
Clark> operating system or Unix."

The 33-MHz Gmicro/300 runs 57,625 Dhrystones/sec, if I remember correctly.
I guess its Dhrystone version is 1.1.
If you define one dhry-MIPS to be 1757 (as IBM does), you get 32.8 MIPS.

SPEC results are not available.

TRON instruction set is very CISCy, but this chip was designed RISCy.
i.e. most primitive instructions run in one cycle (if cache hits) including:
	add @(offset:32,R1), R2		; R2 += memory(R1 + 32_bit_offset) 

One more comment: it has a 2KB data cache as well as a 2KB instruction cache.

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yuhara@flab.fujitsu.co.jp
Masanobu Yuhara
Distributed Processing Section, Optical Networking Systems Laboratory,
Optical Interconnection Division, Fujitsu Laboratories Ltd.