🚀 go-pugleaf

In article <YUHARA.91May20200857@kiko.stars.flab.fujitsu.co.jp>
	yuhara@kiko.stars.flab.fujitsu.co.jp (Masanobu Yuhara) writes:
>
> $B"((JIn <1991May16.182143.15390@murdoch.acc.Virginia.EDU>
>	clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman) said:
>
>Clark> The April 29, 1991 EE Times, page 16, mentions a 33-MHz TRON micro
>Clark> from Fujitsu that supposedly runs at 32 MIPS. No benchmark explanation.
>Clark> It is not intended for workstations, so we will probably never see

  It is for workstations, too:-) Unix is now running on the Gmicro/300 chip.

>Clark> SPEC results for it, and it won't be sold in the U.S. But I am curious
>Clark> to find out if anyone knows anything about the chip and the extremely
>Clark> high ratio of 32 MIPS to 33 MHz for a CISC chip.
>
>The 33-MHz Gmicro/300 runs 57,625 Dhrystones/sec, if I remember correctly.
>I guess its Dhrystone version is 1.1.

  Right, but

>If you define one dhry-MIPS to be 1757 (as IBM does), you get 32.8 MIPS.

Slitly different. The number 32 MIPS comes from 57,625 / 1800, otherwise
you would get 33 MIPS.

Originally, in article <1991May16.182143.15390@murdoch.acc.Virginia.EDU>
	clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman) writes:

>Clever design or another meaningless "MIPS" claim? 

  I think things are HALF/HALF.

  Thanks to its one-cycle-pipeline and Harvard-style cache organization,
the Gmicro/300 executes even a complex instruction somewhat fast as
Yuhara said. On the other hand, it never runs 32 Millions of Instructions
Per Second literally.
  For 32 MIPS only means 32 VAX-MIPS, I would rather say it is not a
Millions of Instructions Per Second but another Meaningless Instructions
Per Second. So, you'd better wait the SPEC marks which will be announced
by the maker.

-- 
							  SAKURAI atsushi
                              E-mail: sakurai@gmd.ed.fujitsu.co.jp