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Article #11738Re: VISC - A way to speed up moto cisc mpu's?
From: Chris Torek
Date: Wed, 22 May 1991 16:03
Date: Wed, 22 May 1991 16:03
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[Context: someone suggested adding/deleting/changing 680x0 instructions for newer 680x0s, with a compatibility mode in the status register or some such.] In article <1991May15.183328.22820@kithrup.COM> sef@kithrup.COM (Sean Eric Fagan) writes: >Uhm, it would probably be better to devote all that chip space to the "RISC" >processor and ship a software emulator. ... Why not just build a multiprocessor system with completely different processors? I.e., ship a system that contains, say, one 68040 and one or more 88x00s. There is no particular reason that the O/S cannot run the proper binary on the proper CPU automatically. Of course, this takes more board space unless the 68040 and 88100 are in the same package (and if that is the case you might have pin problems). -- In-Real-Life: Chris Torek, Lawrence Berkeley Lab CSE/EE (+1 415 486 5427) Berkeley, CA Domain: torek@ee.lbl.gov
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!spool.mu.edu!agate!dog.ee.lbl.gov!elf.ee.lbl.gov!torek From: torek@elf.ee.lbl.gov (Chris Torek) Newsgroups: comp.arch Subject: Re: VISC - A way to speed up moto cisc mpu's? Message-ID: <13445@dog.ee.lbl.gov> Date: 22 May 91 16:03:06 GMT References: <1991May15.110000.25800@Daisy.EE.UND.AC.ZA> <1991May15.183328.22820@kithrup.COM> Reply-To: torek@elf.ee.lbl.gov (Chris Torek) Organization: Lawrence Berkeley Laboratory, Berkeley Lines: 19 X-Local-Date: Wed, 22 May 91 09:03:06 PDT