🚀 go-pugleaf

In article <1991May27.184311.11596@zeno.mn.org>, gene@zeno.mn.org (Gene H. Olson) writes:
> Looking through all the documentation I have been able to find
> on the MIPS processor (Including Gerry Kane's book) I haven't
> found a rule about putting a branch in a branch delay slot.
> 
> There is a very definite rule about doing this in the SPARC
> architecture, probably because its not very useful, and may
> have terrible implications in restarting instructions and so on.
> 
> So I tried to figure why MIPS has not excluded this particular
> combination.

The sequence you describe will work on an HP-PA (Precision, Spectrum)
machine, but not a MIPS machine. The reason is will not work is that I
only put one exception PC on the MIPS architecture, where the HP-PA
has a queue of PC. This means that if an exception were to occur
between the two adjacent branches, the machine state cannot be
recreated after handling the exception. This includes I/O interrupts,
so in general, two adjacent branches do not produce an architecturally
definite result.

Also, the target of a conditional branch is computed via an offset
from the address of the dynamically following instruction, so placing
a conditional branch in a branch delay slot is a tricky proposition.

The only potentially safe combination is to place a conditional branch
in the delay slot of another conditional branch, provided that the
conditions are mutually exclusive.  I don't recall clearly, but even
this combination may have been excluded via the ReservedInstruction
exeception...if not, perhaps it should!

Regards,
Craig Hansen
craig@microunity.com