🚀 go-pugleaf

A while ago there was a thread on building atomic ops
(specifically compare-and-swap) from lower-level primitives.
Some examples were given for MIPS systems using LL and SC
instructions (load-linked and store-conditionally, I believe).
I'd never heard of these, but I assumed that they had been
added post-R3000 for MP synchronization.  Would someone be
kind enough to post a description of their semantics?

(I would look it up, but
 - I have no easy access to recent MIPS references
 - maybe others will find this interesting
 - I'm personally more interested in MP synch. than IEEE FP, so
   maybe we can get some discussion going there.)

Thanks,

Steve