🚀 go-pugleaf

I am having a hard time understanding how the HP PA "Snakes" cache can
operate at 66 MHz using only asynchronous SRAMs external to the CPU.
Referring to the timing diagram below, phi1 and phi2 are the two-phase
66 MHz clocks.  Latch clock is 90 degrees out of phase with phi1,
easily achievable with the 132 MHz input clock.

Assuming that latch clock to address delay is no less than 5 ns, and
data set up is no less than 2 ns, only 8 ns remains for the SRAM access
time, less, if there is any attempt to provide some margin.  Eight ns
access is much faster than any CMOS "off-the-shelf" SRAMs with which I
am familiar.

I suppose the address could be output on the positive edge of phi1,
yielding an extra 7 ns for SRAM access time, but then the address would
change for the next cycle before the data is latched into the CPU.  How
could HP guarantee the SRAM's minimum address to data invalid delay?

Have I made a mistake somewhere?  How does HP do it?


      __________            __________            __________
phi2            \__________/          \__________/          \__________
                 __________            __________            __________
phi1  __________/          \__________/          \__________/

      ____            __________            __________            _____
latch     \__________/          \__________/          \__________/
clock
      _   ___________________   ___________________   _________________
Adr   _XXX___________________XXX___________________XXX_________________
      _____________   ___________________   ___________________   _____
Data  _____________XXX___________________XXX___________________XXX_____


Ed
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
"All right, Doctor, you built this thing!  How do you propose to turn it
off?"                                                   lupin@weitek.com
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++