🚀 go-pugleaf

In article <4755@spim.mips.COM> crisp@mips.com (Richard Crisp) writes:
>>large primary caches (off-chip) for high-performance RISC was generally
>>written off prematurely by some of the industry (or at least according to
>>technical articles published in the last couple of years).  
>>
>
>What Mark doesn't want to say is that HP figured out that they could calculate
>an address in half of a pipeline stage. They simply allow something like
>1 and 1/2 pipe stages for a cache access. 
>-- 
>		    Richard Crisp              crisp@mips.com
>		MIPS Computer Systems        !decwrl!mips!crisp

A similar scheme (although the implementation is proabably different) could
be found if you plan to use the BIT ECL SPARC processors. One could design
large caches with ~10ns access time as the processor cycles at 80MhZ.  

There was a paper published in IEEE MICRO and other places about it.

I don't have the information handy.

renu raman
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   Renukanthan Raman				ARPA:ram@sun.com
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