Article View: comp.arch
Article #12151Re: RISC vs CISC
From: wesley.k.kaplow
Date: Tue, 18 Jun 1991 16:43
Date: Tue, 18 Jun 1991 16:43
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1429 bytes
Well, this was not just another code size measurement. I thought the
original poster request static code information. Well, I wanted to stay
away from any performance data but here goes anyway:
Note: See the previous posting by me to see what the benchmarks are.
DYNAMIC Instruction Count:
Benchmark MIPS Instructions/CRISP Instructions
----------------------------------------------------
BSC 1.56
Dhrystone 1.24
RP 1.50
Static MIPS Instruction Distribution ('cat' + library)
Instr/Opereration % of Distribution
-------------------------------------------------
load/store 26%
branch+Funcall 19%
nop 13%
arith 12%
move reg/load immed 18%
misc 12%
I hope that gives you some more information. It was clear to us, and to
MIPS, that you can sacrifice some characteristics and gain in cycles/instr
efficiency.
with disclamer;
use disclamer;
Wesley Kaplow
AT&T Bell Labs
Whippany, NJ
201-386-4634
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!cbnews!cbnewsl!wkkShow Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!cbnews!cbnewsl!wkk From: wkk@cbnewsl.att.com (wesley.k.kaplow) Newsgroups: comp.arch Subject: Re: RISC vs CISC Keywords: RISC CISC DYNAMIC CODE Message-ID: <1991Jun18.164343.18128@cbnewsl.att.com> Date: 18 Jun 91 16:43:43 GMT Organization: AT&T Bell Laboratories Lines: 38