Article View: comp.arch
Article #12208Re: CISC vs. RISC Code Sizes
From: Wm E Davidsen Jr
Date: Fri, 21 Jun 1991 13:52
Date: Fri, 21 Jun 1991 13:52
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2234 bytes
In article <825@adpplz.UUCP> martin@adpplz.UUCP (Martin Golding) writes:
| This isn't a process of data compression, it's a process of function
| compression, ie, each instruction encodes a series of machine operations.
| For a clear and RISC type example, take a look at your generated assembly
| code, and estimate the resulting size increase if you removed address
| calculation from all of the load/store instructions.
No doubt the code would be tighter if you didn't calculate the
addresses, but it wouldn't *work* very well.
One reason the Intel instruction set code is small is dedicated
registers. By making certain instructions always operate on certain
registers the opcode can be smaller. There's no doubt that a symettrical
instruction set will make compiler writing a lot easier, but that's not
the point here, in terms of code size the occasional mov added to get
something in the right place is usually less than the code saved by lots
of one byte instructions.
Three CISC machines typify approaches to this: Intel has lots of
dedicated registers, Motorola has two classes of register (arith and
address), and the NS32k has totally general purpose registers. Since
each has a diferent number of registers I won't even try to draw any
conclusion from their code size, these are just nice examples for discussion.
--
bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
GE Corp R&D Center, Information Systems Operation, tech support group
Moderator comp.binaries.ibm.pc and 386-users digest.
"I admit I am predjudiced, I can't stand bigots." -me
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!crdgw1!crdos1!davidsenReferences:
<1991Jun18.132315.8202@cbnewsl.att.com> <1991Jun18.152303.1889@rice.edu> <3436@crdos1.crd.ge.COM> <825@adpplz.UUCP>Show Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!crdgw1!crdos1!davidsen From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) Newsgroups: comp.arch Subject: Re: CISC vs. RISC Code Sizes Keywords: CISC RISC Size CRISP MIPS R3000 Message-ID: <3452@crdos1.crd.ge.COM> Date: 21 Jun 91 13:52:38 GMT References: <1991Jun18.132315.8202@cbnewsl.att.com> <1991Jun18.152303.1889@rice.edu> <3436@crdos1.crd.ge.COM> <825@adpplz.UUCP> Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen) Organization: GE Corp R&D Center, Schenectady NY Lines: 29