Article View: comp.arch
Article #12224Re: Faster busses are hard; can we do wider?
From: Alan L. Scheinine
Date: Sat, 22 Jun 1991 01:36
Date: Sat, 22 Jun 1991 01:36
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> The Cinch connector, and our chip carrier have enough extra feed
> throughs that we can use the packaging as both the chip-to-board
> connections, and the board-to-board connections. This lets us dispense
> with the backplane entirely; all signal flow between boards is very
> short wire length, and can have good impedance matching.
[...and more interesting information.]
I have pondered parallel designs and interconnection schemes
for many years. Within the universe of different interconnection
schemes there are qualitatively different versions, i.e. not obviously
isomorphic. Nonetheless, when in comes down to implementation, every
scheme seems to be roughly the same speed (very roughly). (Of
course, any given interconnection scheme has algorithms for which it
is well matched.) I've concluded that one essential area the needs
progress is the connection hardware. For a long time, I expected that
a very clever interconnection topology would result in a great leap
forward in parallel computers. Now I think that interconnection
topology ideas are adequately clever, no further leaps are needed.
As mundane as it may be, tiny connectors are the key technology for
further great leaps in parallel computing.
My words have not been chosen carefully and my generalizations
have many exceptions. Please understand that I am not trying to
present an overall philosophy. Rather, I am presenting a notion for
the purpose of saying:
Let's hear more about tiny connector hardware! It is important.
Alan Scheinine
u10534@uy.ncsa.uiuc.edu
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!zaphod.mps.ohio-state.edu!hobbes.physics.uiowa.edu!maverick.ksu.ksu.edu!ux1.cso.uiuc.edu!mrlaxa.mrl.uiuc.edu!scheinin From: scheinin@mrlaxa.mrl.uiuc.edu (Alan L. Scheinine) Newsgroups: comp.arch Subject: Re: Faster busses are hard; can we do wider? Keywords: Fuzzballs, Interconnection topology Message-ID: <1991Jun22.013602.18456@ux1.cso.uiuc.edu> Date: 22 Jun 91 01:36:02 GMT Sender: usenet@ux1.cso.uiuc.edu (News) Reply-To: u10534@uy.ncsa.uiuc.edu (Alan L. Scheinine) Organization: Department of Physics, University of Illinois, Urbana Lines: 31 Originator: scheinin@mrlaxa.mrl.uiuc.edu