Re: Branchless conditionals

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Article #12268

#12268

From: Jim Garside
Date: Wed, 26 Jun 1991 10:01

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Since no one has mentioned it, the ARM - a modern RISC processor - has
conditional execution of *all* its instructions.

Jim Garside

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References: <1991Jun14.173510.22510@dg-rtp.dg.com> <32580036@hpcuhe.cup.hp.com> <13947@mentor.cc.purdue.edu>

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!spool.mu.edu!uunet!mcsun!ukc!mucs!jdg
From: jdg@cs.man.ac.uk (Jim Garside)
Newsgroups: comp.arch
Subject: Re: Branchless conditionals
Message-ID: <2795@m1.cs.man.ac.uk>
Date: 26 Jun 91 10:01:11 GMT
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References: <1991Jun14.173510.22510@dg-rtp.dg.com> <32580036@hpcuhe.cup.hp.com> <13947@mentor.cc.purdue.edu>
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