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Article #12300Re: 64 Bit addressing on R4000?
From: William.Lott
Date: Sun, 30 Jun 1991 21:32
Date: Sun, 30 Jun 1991 21:32
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1646 bytes
William.Lott@cs.cmu.edu writes: > jfc@athena.mit.edu (John F Carr) writes: > ... > > l r3,0x4(r2) # 4(r2) is &x > ... > > I don't know how many MIPS opcodes are unused -- is there room to add two > > more instructions with format reg,reg,disp16? If not you'll need more than > > 4 instructions to load an address using the current method. > > > > -- > > John Carr (jfc@athena.mit.edu) > > Isn't that just an add? (Or, in the MIPS case, an ``addu?'') Why > would you need additional instructions? > > -William Lott Oops. I guess I get the bozo award for the day. I had originally though that you were asserting that they needed an load-effective-address instruction, which is not needed, because it is just an addu. On re-reading your post, I realized the two needed instructions were load and store 64 bits. I don't have my MIPS R[23]000 book with me, but I'm pretty sure they have room for them. -William Lott
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!magnus.acs.ohio-state.edu!usenet.ins.cwru.edu!gatech!udel!rochester!pt.cs.cmu.edu!o.gp.cs.cmu.edu!andrew.cmu.edu!<UNAUTHENTICATED>+ From: William.Lott@cs.cmu.edu Newsgroups: comp.arch Subject: Re: 64 Bit addressing on R4000? Message-ID: <QcPYrpO00jeiAOWVMX@cs.cmu.edu> Date: 30 Jun 91 21:32:37 GMT References: <14900025@hpdmd48.boi.hp.com> <880@taniwha.UUCP> <MEISSNER.91Jun28105156@tiktok.osf.org>, <1991Jun29.163857.14050@athena.mit.edu>, <4cPX7om00jeiMOGHdQ@cs.cmu.edu> Organization: Carnegie Mellon, Pittsburgh, PA Lines: 25 In-Reply-To: <4cPX7om00jeiMOGHdQ@cs.cmu.edu>