🚀 go-pugleaf

pradeep@watson.ibm.com (Pradeep Dubey) writes:

>Hello Everyone,
>Are there announced machines (specially micros) with
>some conditional assignment instruction.  I mean
>instruction such as the following:

>MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */

>where, c1 refers to some result of some previous compare.

>Any pointers to such machines or any quantitative evaluation
>of usefulness of this instruction in the specific context
>of some machine would be appreciated.

On the ARM processors all instructions are conditional, so you can
have a MOV<C> R1,R2, which will move R2 to R1 if the condition is
true. To simulate the 3-argument MOVCond you describe, the sequence

	MOV    R1,R3
	MOV<C> R1,R2

or

	MOV<C>  R1,R2
	MOV<~C> R1,R3

can be used. In present ARM implementations these are equally fast.

Digitals Alpha RISC also have conditional moves, as does the proposed
new generation of SPARC. HPs PA-RISC allows some instructions to
conditionally nullify the next instruction. So a 3-argument
conditional move can be implemented with something like

	--- 	  skip if C	\ previous instruction that determines C
	MOV R1,R3 skip always
	MOV R1,R2

with a disclaimer about notation. The idea is that when C is true, the
next instruction is nullified, so MOV R1,R2 is executed. When C is
false, MOV R1,R3 is executed and the MOV R1,R2 nullified.

The designers of these processors obviously felt that it was worth the
effort. It is especially interesting to see that conditional moves are
added to the new SPARC architecture even though they were not part of
the original design. It is difficult to give a good quantitive measure
of the usefulness, but one could try to count the frequency of such
instructions in optimized code.

	Torben Mogensen (torbenm@diku.dk)