Article View: comp.arch
Article #12346Re: Harvard Architecture
From: Paul Ries
Date: Tue, 26 Jan 1993 01:36
Date: Tue, 26 Jan 1993 01:36
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savel@hal.COM (Bharat Baliga-Savel) writes: >hmmm! i was under the impression that it was specifically a separate >Instruction Cache and Data Cache. >-- I think a lot of people use it that way now, but the term predated the use of caches. For example, when I was back at Intel many of the microcontrollers had a EPROM instruction store and a data RAM array... neither memory could be used for another purpose. This was called a Harvard architecture at the time (though I'm sure by that time caches existed). -- -Paul Ries DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: pries@mti.sgi.com Phone: 415-390-4481 USPS: Silicon Graphics Computer Systems, MS 10L-135 2011 N. Shoreline Blvd, Mountain View, CA 94039-7311
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Path: arc1-ca.pugleaf.net!sparky!uunet!olivea!sgigate!sgi!mips!meter!pries From: pries@mti.sgi.com (Paul Ries) Newsgroups: comp.arch Subject: Re: Harvard Architecture Message-ID: <pries.728012209@meter> Date: 26 Jan 93 01:36:49 GMT References: <1k1ljgINNf76@gorn.hal.com> Organization: Silicon Graphics, Inc. Lines: 17 NNTP-Posting-Host: meter.mti.sgi.com