🚀 go-pugleaf

Nitezki@NiDat.sub.org (Peter Nitezki) writes:

>In article <2B51D662.29834@news.service.uci.edu> jtien@venice.eng.uci.edu  
>(Joe Tien) writes:
>> 
>> Could someone direct me to a good definition of the harvard
>> architecture? Is it dual memory port (each with own set of address and
>> data bus) or is it just dual bus (separate address and data bus used for
>> both instruction and data.)
>> 
>> If possible, I'd prefer some type of reference I can use in my paper,
>> not that I don't trust the infinite wisdom of the net. :-)
>> 

>Basically the second!

>Once it was called Zuse architecture (then von Neumann took over).
>After a while it got a writable control/instruction (as you like it) store  
>and was called Harvard architecture; just to take over in the modern DSP  
>designs.

>Just as a start for argument ;-)


My understanding is that a Harvard architecture consists of two _seperate_
buses, one for data and one for instructions.  I have no references at
hand.  But, Motorola used the term in their lititure describing the internal
buses on the 030 or 040.
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Emil Rojas  emil@shell.portal.com (408) 973-0603
Cognisys Software Systems Development
San Jose, CA 95129