🚀 go-pugleaf

gss@ilx018.intel.com (Shavit Amir) writes:
] Pradeep Dubey (pradeep@watson.ibm.com) wrote:
] : Hello Everyone,
] : Are there announced machines (specially micros) with
] : some conditional assignment instruction.  I mean
] : instruction such as the following:
]
] : MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
]
] : where, c1 refers to some result of some previous compare.
]
] The above instruction is a 4 operand instruction, as the condition code is
] another implicit source operand. The best way to perform a conditional move
				       ^^^^
] is to have compares set or clear all the bits in a register.
] Once that is done, conditional moves are simple.
]
] AND R1, R2 -> R4    /* R1 containes the condition code */
] ANDNOT R1,R3 -> R4

? Why is
	TEST<cc>, tsrc1, tsrc2, tdst
	AND       tdst, msrc1, mdst
	ANDNOT    tdst, msrc2, mdst

"best" compared to

	TEST        tsrc1, tsrc2
	SELECT<cc>  msrc1, msrc2, mdst

Yes, the first avoids the CC-bits bottleneck, but multiple CCs could do that
without consuming an entire register (a la RS6000). It uses three intructions
instead of two, so it seems a loss to me.

Yes, the latter uses three inputs and one output, where one input
is the CCs. However, add-with-carry does this too, and most architectures
already have it, so it can't be a big deal.
--
Dennis O'Connor			doconnor@sedona.intel.com