Article View: comp.arch
Article #12360Re: DSP chip design
From: Joe Buck
Date: Thu, 28 Jan 1993 00:27
Date: Thu, 28 Jan 1993 00:27
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1064 bytes
In article <49154@ogicse.ogi.edu> stever@anago.cse.ogi.edu (Steve Rehfuss) writes: >DSP chips are optimized for a certain class of algorithms, relative to >general purpose microprocessors. What's a good reference on the architectural >tradeoffs being made vis-a-vis the class of algorithms targeted? Edward Lee did a series of two articles for the IEEE's ASSP Magazine; "Programmable DSP Architectures, Part I" appears in the October 88 issue and part 2 appears in the January 89 issue. This series has a lot of information on DSP architectures and why they are the way they are. -- Joe Buck jbuck@ohm.berkeley.edu
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Path: arc1-ca.pugleaf.net!sparky!uunet!ukma!bogus.sura.net!howland.reston.ans.net!spool.mu.edu!agate!forney.berkeley.edu!jbuck From: jbuck@forney.berkeley.edu (Joe Buck) Newsgroups: comp.arch Subject: Re: DSP chip design Date: 28 Jan 1993 00:27:06 GMT Organization: U. C. Berkeley Lines: 18 Distribution: world Message-ID: <1k798q$fsd@agate.berkeley.edu> References: <49154@ogicse.ogi.edu> NNTP-Posting-Host: forney.berkeley.edu