🚀 go-pugleaf

Conventionally memory has been implemented in one hole block of address
decoded ramchips and bus. The continuous bandwidth of memory chip is
however limited and can't supply memory fast enough for fast processor
without expensive cache systems.

Nowadays we are reading the news of 64 Mbit RAM chip implementations
etc. The memory bandwidth is however still very limited. So how could it
be speeded up.

1) direct mapped cache on memory chip itself and very wide or multiple
paths from memory cells to output pins.

COMMENT: This is quite obvious way, but I have not info about the
economics of this kind of thing. So please give info: how costly is say
256 bit wide buss inside chip in number of memory cells? How about
having four segments each with 64 bit path of access (possibly no sense
because there mayby is no advantage otherwise than lower chip count
compared to using four chips) ? How about massively parallel arrangement
with say 1024 parts of chip with each having its very small direct
mapped cache?

2) Having multiple memory segments with own memory buss mapping
consecutive memory addresses in interleave scheme to different memory
systems.  So with n segments we have refense to same segment only every
nth cycle in typicall case. Say we have 200 MHz processor and 50 memory
systems, then we have typical address frequency of 4 MHz per block, like
in my Acorn Archimedes A310 which uses 4 MHz clock, but uses burst mode
in 8 MHz. If we offsett the memorysystems to operate in different 200
Mhz cycles (1st block cycles 0,50,100,150, 2nd 1,51,101,151 or any fifty
spaced partition of cycle numbers which ever allocation seemed
sensible) and combine them in processor we get agregate bandwidth 200
MHz practically allway. As long as we keep signals from memory systems
short enough i.e. 1/200MHZ long, it would seem to me that there should
be no problem in having memory system match or eaven exceed any given
clock frequency. Where has these kind of memory system implemented and
why have I not heared of them? Actually massively parallel computer is
quite similar to this kind of memory architecture.
-- 
Tony Veijalainen	e-Mail: Tony.Veijalainen@helsinki.fi (preferred)
 		(finger veijalai@cc.helsinki.fi for more information)