🚀 go-pugleaf

I'm pretty sure this didn't make it out last time 
(cross posting problems- why comp.sys.intel?), so here it is again:


>pcg@aber.ac.uk (Piercarlo Grandi) writes:
>>This is another reason for which I think hyperscalar is premature:
>>a vector instruction has the very nice property that it implies a very
>>definite memory access pattern, 

>	This is one reason I've been advocating smarter caches, particularily
>the ability to do predictive pre-fetching.  There are a couple of ways to
>set this up:

>1.	Instruction sets address, bound, and perhaps amount to fetch....

This sounds just like the WM machine. It has an instruction that says: start a
vector fetch from this base with this stride and put it in this FIFO. The FIFO
is accessed as a GPR, which any instruction can use (including, presumably, another
load for gather/scatter. There are two read FIFOs and a write FIFO in the WM design.

The HPPA has some bits in the short displacement load/store
instructions that can be used for cache hints of the type you want- I
think only one combination has been defined so far
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Allen J. Baum		Apple Computer		baum@apple.com, abaum@armltd.co.uk