🚀 go-pugleaf

This is my third posting in my cracy thoughts series :-)

There is common trend towards harwardizing the memory lane by separating
instructions and data to separate caches with own bus to other parts of
CPU.

On the other hand FPU-units that appear more and more are in modern big
CPU:s are quite far conceptually from other operations.  I have
suspision that FP-arithmetic tends to cluster quite heavily, and because
of traditional efficiency thinking and fixed number arithmetic in
business applications some big parts of programs are integer only (not
much FP-operations in interupt code for example :-). 

So have somebody researched the havoc FPU-instructions make to general
data cache? Is there possible advantage of having FP-number (with
separate bus to FPU-register file) and fixnumber caches with advantages
outdoing the cost on CPU (like diminiching the general cache size, is
this over specialization?). 

I am very inspired about Dick Pountains articles on ARM architecture in
Dec 92 (ARM6) and Jan 93 (asyncronic ARM6) (Mayby it has something to do
with the thing that I own ARM2 based ancient Acorn Archimedes A310 have
something to do with it :-) Anyone of you real experienced experts care
to comment on these especially the unclocked VLSI design.  I can see
some RISC -perspectives attacking the new wind mill: enormous clock
circuitery in "More Risc Than Your Risc" Alpha processor.  Jan 93 ibid
article mentiones 1/4 of chip area cost of clock circuitery in current
Alpha architecture implementation.  Care to comment on architectual
suitability of asyncronism instead of superpipelining in Alpha
architecture.  I do like Alpha very much thank you, but this one sided
view of architectual development toward Cisc-scale complexity of
pipeline magic and clocking instead of simple asyncronic circutery is
mayby mistake, is it not?


-- 
Tony Veijalainen	e-Mail: Tony.Veijalainen@helsinki.fi (preferred)
 		(finger veijalai@plootu.helsinki.fi for more information)