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Article #12452

Re: uniprocessor design ceiling

#12452
From: Malcolm Shute
Date: Wed, 06 Jan 1993 11:59
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In article <1993Jan3.215458.7960@athena.mit.edu> solman@athena.mit.edu (Jason W Solinsky) writes:
>If (as I have been led to believe) there
>exists a linewidth which is large enough for yield to be effectively 100%,
                                                          ^^^^^^^^^^^
You quite rightly recognise that it never exactly reaches 100%...
it's just an exponential curve which at some arbitrarily defined 'knee'
you decide to treat it as being negligably close to 100%.
So... if you're going to do something drastic, like multiplying the number
of process steps by a couple of hundred, you will not be surprised to find
the position of this knee moving.
[I've never really understood how people manage to read 0.7V as the position
of the knee of the exponential function which is supposed to characterise
the IV curve for a silicon PN junction... you only need to get a magnifying
glass out, and the point at which the curve really starts to break away from
the I-axis moves :-]

>why hasn't anybody attempted to build a very tall, large line width chip?
>Is the problem a difficulty in creating monocrystaline Si above the substrate?
>Are problems with planarization cumulative such that working with too many
>levels becomes impossible?
                                                  -k
It is tempting for me to write:  Y = ( 1 + A.D/k )
where:  Y = circuit yield
        A = circuit area
        D = fault density
        k = number of process steps

It is one of those theoretically-reasoned models which abound in yield modelling.
Unfortunately, Stapper indicates that, tempting though its arguments are, it
bears no correlation with any experimental results that he has gathered.
Instead, he, and most in the industry, appear to favour the negative binomial
model, which appears:                   -a
                       Y = ( 1 + A.D/a )
Where 'a' is an empirically measured 'clustering coefficient'.  It is going to
have the effect of rising to kill your 1000-processing-step 3D process, but not
in quite the obvious linear way that the Y=(1+AD/k)^(-k) would have suggested.

[If you want to persue Stapper's excellent review paper on yield models, it is:
Stapper, C.H. (1989).
'Fact and fiction in yield modeling',
"Microelectronics Journal",
Vol. 20(1), pp 129-151.]
--

Malcolm SHUTE.         (The AM Mollusc:   v_@_ )        Disclaimer: all
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Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!uknet!mucs!mshute
From: mshute@cs.man.ac.uk (Malcolm Shute)
Newsgroups: comp.arch
Subject: Re: uniprocessor design ceiling
Message-ID: <7125@m1.cs.man.ac.uk>
Date: 6 Jan 93 11:59:03 GMT
References: <2340@sousa.tay.dec.com> <1ho4g1INNgac@nigel.msen.com> <1993Jan3.215458.7960@athena.mit.edu>
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