Article View: comp.arch
Article #12469Re: How does an R4000-style cache work?
From: Andrew Wolfe
Date: Thu, 07 Jan 1993 21:10
Date: Thu, 07 Jan 1993 21:10
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I received a rather complete explanation written by John Mashey and apparently posted to comp.arch about 18 months ago. Summary: -------- Writes go to a store buffer (2 deep) where they are held until free cache cycles. Subsequent stores only use the cache tag RAM - not the cache data RAM, thus data is retired from the store buffer during later stores at the same rate that data enters the store buffer - therefore, the store buffer never overflows. Of course, the store buffer also empties during non-memory operations. Accesses to data still in the store buffer can cause a stall. -- -------------------------------------- Andrew Wolfe Assistant Professor Department of Electrical Engineering Princeton University
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Newsgroups: comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!princeton!moo!awolfe From: awolfe@moo.Princeton.EDU (Andrew Wolfe) Subject: Re: How does an R4000-style cache work? Message-ID: <1993Jan7.211014.3496@Princeton.EDU> Originator: news@nimaster Keywords: Write-back Cache Sender: news@Princeton.EDU (USENET News System) Nntp-Posting-Host: moo.princeton.edu Organization: Princeton University References: <1993Jan6.235455.25425@Princeton.EDU> <1993Jan7.201733.16338@csrd.uiuc.edu> Date: Thu, 7 Jan 1993 21:10:14 GMT Lines: 25