Article View: comp.arch
Article #12509Re: Asynchronous acorn.
From: Stefan Monnier
Date: Fri, 08 Jan 1993 23:43
Date: Fri, 08 Jan 1993 23:43
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I've read about the 'previous' asynchrous processor (but non-commercial (especially lacking interrupts)), but I just can't find any report on the ARM. Is there some source of information about it (I've got the tiny BYTE article, but that's FAR too general) ? Or is it too early ? (I'm especially interested in the way they handle interrupts) Thanks for any hints, Stefan
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arc1-ca.pugleaf.net!sparky!uunet!cis.ohio-state.edu!zaphod.mps.ohio-state.edu!howland.reston.ans.net!sol.ctr.columbia.edu!emory!ogicse!das-news.harvard.edu!cantaloupe.srv.cs.cmu.edu!monnierReferences:
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Path: arc1-ca.pugleaf.net!sparky!uunet!cis.ohio-state.edu!zaphod.mps.ohio-state.edu!howland.reston.ans.net!sol.ctr.columbia.edu!emory!ogicse!das-news.harvard.edu!cantaloupe.srv.cs.cmu.edu!monnier From: monnier+@cs.cmu.edu (Stefan Monnier) Newsgroups: comp.arch Subject: Re: Asynchronous acorn. Keywords: How do they interface the new asynchronous acorn with the main memory ? Is the cache asynchronous too ? Message-ID: <C0K78E.7AA.2@cs.cmu.edu> Date: 8 Jan 93 23:43:26 GMT Article-I.D.: cs.C0K78E.7AA.2 References: <1ijo9qINNhne@mailgzrz.TU-Berlin.DE> Sender: news@cs.cmu.edu (Usenet News System) Organization: School of Computer Science, Carnegie Mellon Lines: 12 Nntp-Posting-Host: j.gp.cs.cmu.edu