🚀 go-pugleaf

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We appreciate your suggestions given to us to consider SCI 
or one of it's derivatives (instead of Anet) as a solution 
for PC I/O interconnects.  However, based on our 
interpretations of information we have, SCI and RamLink do 
not provide as low cost a solution as we desire.  Here is 
why...
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"Many features are incorporated in SCI to support 
multiprocessor coherent and message-passing operations" [an 
excerpt from one of David Gustavson's SCI articles].  We 
agree.

The problem that was addressed with Anet is much more 
limited in scope than the problem that SCI is intended to 
solve.  All we ask of Anet is that it provides a mechanism 
for attaching I/O devices to the system.  With this more 
limited scope, we were able to develop an interface that is 
very low cost while providing performance adequate for a 
wide range of I/O needs, up to and including graphics/video.

Although much emphasis has been placed on low pin counts in 
all of our correspondence, getting low pin counts is not a 
sufficient cost metric.  It has been explained to us by 
those knowedgeable about SCI that SCI implementations range 
from 50K to 100K gates in complexity.  An Anet inteface can 
be done with <1K gates for a simple, slave-only device (e.g. 
a serial port controller) to around 10K gates for a multi-
request mastering device (e.g. an FDDI controller.)  This 
magnitude of difference is noticable no matter how 
inexpensive one can purchase ASICs.

Another problem we have with SCI is its applicability in 
mobile applications.  An SCI link is always "busy" 
transferring either information or idle packets (to 
synchronize the nodes), i.e., there is a constant power 
drain due to continuously switching devices.  Athough Anet 
requires a clock, the total power in a quiescent Anet 
interface is much lower than one for SCI.  To further reduce 
power consumption, the Anet protocol allows data buffers to 
be power gated when data is not actually being transferred 
and a further portocol allows the clock to be stopped to 
reduce power even more.

It is interesting to note that one of the SCI design goals 
was Interface - "a standardized open communication 
architecture that allows products from multiple vendors to 
be incorporated into one system and interoperate smoothly" 
[IEEE Micro, Feb. 1992, pg. 11] - and yet there are a few 
different physical layers defined and more standards are on 
their way.  We can see the usefulness of the parallel (P18) 
and the serial (S20) protocols for different distances.  We 
can also see why RamLink (P1596.4) simplified SCI's original 
protocols significantly - primarily to interface to memory 
and not to worry about the MP issues.  This is exactly what 
we were trying to point out - SCI has a lot of fat for low 
cost I/O applications and RamLink still is not lean enough.  
We tried to define Anet physical layer to be consistent 
across different performance systems.  An Anet card should 
work in a very small computer as well as in a multiprocessor 
server.

We actually view Anet and SCI as being complementry 
protocols just as we see both Anet and SCI as being 
complementry to existing inter-box protocols (e.g. Ethernet, 
FDDI, SCSI, etc.)  We don't believe that there is a single 
connection mechanism that is optimal both for a multi-
processing CPU/memory core and for I/O devices (especially 
I/O devices on something like a PDA.)  So, different 
problem, different solution.